Semiconductor memory device for shortening the set up time and hold time of control signals in synchronous DRAM
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United States of America Patent
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Nov 16, 1999
Grant Date -
N/A
app pub date -
Nov 22, 1996
filing date -
Nov 29, 1995
priority date (Note) -
Expired
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Abstract
Shortening setup and hold times by equalizing the signal propagation delay time between input buffer circuits and D-F/F circuit to which are supplied command control signals CSB, RASB, CASB, and WEB supplied from a plurality of external terminals, and synchronizing these command control signals with the internal clock signal ICLK, batch loading these into D-F/F circuit and holding this signal, sending it from decode circuits after decoding, and latching it with latch circuits by means of internal clock delay signal ICLKD generated and delayed by internal clock signal ICLK thus being capable of shortening setup time and hold time in a synchronous DRAM.
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