Synchronous read only memory device
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United States of America Patent
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Nov 16, 1999
Grant Date -
N/A
app pub date -
Jul 29, 1998
filing date -
Jul 29, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A read only memory device having a given burst length comprises: a memory cell array having a plurality of memory cells, each of the memory cell storing a data bit; a pass gate circuit having a plurality of pass gate blocks assigned to a plurality of bit lines coupled to the memory cells; a sense amplifier circuit having a plurality of sense amplifiers connected to the pass gate blocks with a given ratio thereof; decoding means for causing the pass gate circuit to transfer a given number of the data bits from the memory cells to the sense amplifier circuit; and means for receiving the data bits from the sense amplifier circuit and for outputting a plurality of data bits corresponding to the burst length in a given operation mode. The memory device preferably conducts in a sequential mode or interleave mode, with a pipelined data output configuration according to the burst length.
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