Arrangement at an image processor
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United States of America Patent
Stats
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Nov 9, 1999
Grant Date -
N/A
app pub date -
Feb 14, 1997
filing date -
Jul 22, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention relates to a parallel processor containing a number of processor elements of the same type which are integrated on one and the same semiconductor chip. The processor is of the type that allows image and signal processing of the information stored in the processor element. The device contains a unit block (3) for each processor element and is characterized in that each unit block comprises at least two incrementing units (1a, 1b) which are designed to add a signal supplied to the unit block and a signal which originates from an incrementing unit corresponding to the respective unit in the closest preceding unit block in every direction of the processor element matrix. Every unit block (3) further contains at least one logical unit (2) which is designed to perform Boolean logic operations on the signals received from the incrementing units of the unit block.

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- 15 United States
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SICK IVP AKTIEBOLAG | WALLENBERGS GATA 4 LINKOEPING 583 35 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Forchheimer, Robert | Linkoping, SE | 17 | 225 |
strom, Anders | Linkoping, SE | 10 | 250 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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