Family

Loading Family data...

• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
INTEL CORPORATION	2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

• H04N:PICTORIAL COMMUNICATION, e.g. TELEVISION

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Goldschmidt, Iti Jean M	San Jose, CA	1	917
# of filed Patents : 1 Total Citations : 917
Hackson, David N	Sunnyvale, CA	30	3172
# of filed Patents : 30 Total Citations : 3172
Moore, Kenneth Alan	Fremont, CA	18	2826
# of filed Patents : 18 Total Citations : 2826
Shah-Nazaroff, Anthony A	Santa Clara, CA	50	3494
# of filed Patents : 50 Total Citations : 3494
Watts, E Michael	Morgan Hill, CA	4	1026
# of filed Patents : 4 Total Citations : 1026
Williams, Christopher D	Soquel, CA	56	3372
# of filed Patents : 56 Total Citations : 3372

Cited Art Landscape

Load Citation

• No Cited Art to Display

Loading Cited Art Landscape...

Patent Citation Ranking

• 917 Citation Count
• H04N Class

• 97.87 % this patent is cited more than
• 26 Age

Forward Cite Landscape

Load Citation

• No Forward Cites to Display

Loading Forward Cite Landscape...

Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

Full Text

US Patent No: 9874925

Method and apparatus for a zero voltage processor sleep state

---

Abstract

---

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

---

 

---

Description

---

Claims

---

Claims data not available

---

Legal Events

 

• AS2022
• MAFP2020
• I2018
• STCF2018
• P2016
• F2015

Date	Code	Event	Description
Jul 18, 2022	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:061175/0176 Owner name: TAHOE RESEARCH, LTD., IRELAND Effective Date: Jul 18, 2022
Dec 07, 2020	MAFP	MAINTENANCE FEE PAYMENT	free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY year of fee payment: 4
Jan 23, 2018	I	Issuance
Jan 03, 2018	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Apr 07, 2016	P	Published
Dec 11, 2015	F	Filing