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Abstract

A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block. A subsequent rising edge of a delayed version of the clock signal is employed by a reset unit to generate a precharge signal which charges the evaluate and evaluate complement signal back to their precharge logic state. The data out and data out complement signals are correspondingly discharged, producing the falling edge of the output pulse and terminating assertion of the precharge signal. The dynamic pulse register is thus able to generate a pulse output in a single logic stage employing a standard clock signal. The speed of the pulse register may be advantageously increased without introducing the complexity of an early clock signal.

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