Electron beam drawing process
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United States of America Patent
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Oct 26, 1999
Grant Date -
N/A
app pub date -
Sep 3, 1997
filing date -
Sep 5, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
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