Semiconductor memory device with reduced read disturbance
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United States of America Patent
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Oct 19, 1999
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N/A
app pub date -
Mar 21, 1997
filing date -
Mar 21, 1997
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Abstract
An apparatus and method for use in a semiconductor memory device to reduce or eliminate read disturbance effects. Select signals supplied from one or more address decoders to a memory array are used to select particular wordlines and bitlines of the array. Read disturbance effects can arise when select signal voltage stresses are applied for extended periods of time to terminals of memory cells coupled to the selected wordlines and bitlines. The memory device therefore includes circuitry to detect a transition in at least one of the select signals, and to generate a timing signal from the detected transition. The timing signal is supplied to the address decoders and directs the decoders to deselect previously-selected wordlines and bitlines at a predetermined time after the transition. The predetermined time is chosen to be greater than or equal to the total time required to read data reliably from the selected memory cells before the deselection of the wordlines and bitlines. The deselection ensures that voltage stresses will not be applied to selected memory cells for extended periods of time, and the contents of the cells are therefore not unintentionally altered due to read disturbance effects.
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