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Abstract

A structure and method for high density programmable logic device (PLD) testing, programming, and verification is disclosed. The device employs non-volatile memory cells, such as electrically erasable programmable ROM (EEPROM), as its programmable elements. The structure and method allow the PLD to work in the normal operation state and also in a number of utility states. In normal operation state, the PLD performs the configured logic function as programmed by the user. In utility states, the PLD can be programmed, verified and tested. A state machine and a decoder are used to perform these procedures. They include bit program (write), verify (read), bulk program (write all), bulk erase (erase all), checker board and inverse checker board program, cell current test, address decode test, softwrite test and logical function test data preload. All the utilities are in a serial algorithm and are controlled by an internal state machine, which needs as few as four dedicated pins to interface with the PLD proper. In cell current test state, an additional dedicated external pin is used to supply a control voltage to a floating gate transistor in order to control the cell current. Serial logic circuits are designed to meet this test requirement.

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First Claim