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Abstract

A class D amplifier includes a scaled clock generator for generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal; and a PCM to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal. The amplifier preferably includes an input circuit for generating the N bit PCM signal from an input signal, and a truncation circuit for truncating the N bit PCM digital signal to the K MSBs PCM signal. The PWM output signal may be coupled to a switch driver which, in turn, is coupled to one or more output switches. The amplifier uses a practically implemented reference clock without the drawbacks associated with a conventional noise shaping filter. The scaled clock generator may be provided by a divider having a first input receiving the N bit digital input signal and a second input receiving the K MSBs signal for generating a clock scale ratio signal. The scaled clock generator may also include a reference clock, and a numerically controlled clock connected thereto for producing the scaled clock signal. The scaled clock generator may further include a bias circuit for inputting a bias value to the divider so that a numerator thereof is greater than zero.

First Claim