Computer memory system having programmable operational characteristics based on characteristics of a central processor
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United States of America Patent
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Sep 14, 1999
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N/A
app pub date -
Oct 5, 1993
filing date -
Aug 6, 1990
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Abstract
A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.
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