Distributing video buffer rate control over a parallel compression architecture

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United States of America Patent

PATENT NO 5949490
SERIAL NO

08889561

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Abstract

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An algorithm for distributing video buffer rate control over a parallel compression architecture uses parallel processors to first compute complexity measures for each macroblock of a current picture. Based upon the complexity measures a master controller determines target rates for each slice of the current picture. A set of slices are then encoded in parallel by the parallel processors acting as microrate controllers, each slice being encoded based solely upon its own target rate. After the set of slices are encoded, the target rates are adjusted for the remaining slices based upon the actual rates from the encoded slices, and the next set of slices is encoded in parallel based upon the updated target rates. After each macroblock within a slice is encoded, a VBV fullness check is made to detect if VBV overflow or underflow is likely to occur. In such an event emergency action is taken to prevent such overflow or underflow. In this manner message passing overhead between the master controller and parallel processors is minimized while retaining the benefits of parallel processing.

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Patent Owner(s)

Patent OwnerAddress
GRASS VALLEY (US) INC400 PROVIDENCE MINE ROAD NEVADA CITY CA 95959

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Borgwardt, Peter A Portland, OR 8 103
Horne, Caspar Santa Clara, CA 7 556

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