Method and system for efficient register sorting for three dimensional graphics
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United States of America Patent
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Sep 7, 1999
Grant Date -
N/A
app pub date -
Mar 31, 1997
filing date -
Mar 31, 1997
priority date (Note) -
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Abstract
A polygon vertex sorting circuit for a three dimensional graphics computer system. The system of the present invention includes a swap configuration circuit coupled to receive a plurality of vertex address corresponding to a plurality of vertices of a polygon. The swap configuration circuit is coupled to an address input bus to receive the plurality of vertex addresses. An address output interface circuit is coupled to the swap configuration circuit. The address output interface circuit interfaces the output of the swap configuration circuit with an address output bus. A control circuit is coupled to the swap configuration circuit and the output interface circuit. The control circuit sorts the plurality of vertices by configuring the swap configuration circuit and the address output interface circuit to output a swapped vertex address via the address output bus in response to receiving one of the plurality of vertex addresses via the address input bus.
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