Method of planarization of an intermetal dielectric layer using chemical mechanical polishing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5948700
SERIAL NO

08650694

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method of planarizing integrated circuit wafers using chemical mechanical polishing with an automatic end point and without using an etchback step. An electrode pattern is formed in a layer of soft metal, such as Al/Cu/Si, capped with a layer of hard metal such as tungsten. A layer of first oxide, a layer of spin on glass, and a layer of second oxide are formed over the electrode pattern. The layer of first oxide, the layer of spin on glass, and the layer of second oxide are then planarized using chemical mechanical polishing. The hard metal cap on the electrode pattern can not be removed by the chemical mechanical polishing and forms an automatic end point. The electric current powering the motor driving the chemical mechanical polishing changes when the hard metal cap is reached and this change can be used to detect the end point.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
CHARTERED SEMICONDUCTOR MANUFACTURING PTE LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738406

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Lap SF, CA 159 4868
Zheng, Jia Zhen Singapore, SG 96 1945

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation