Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal
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United States of America Patent
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Aug 31, 1999
Grant Date -
N/A
app pub date -
Jan 23, 1998
filing date -
Jun 18, 1997
priority date (Note) -
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Abstract
An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.
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