Self-biased power isolator system
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United States of America Patent
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Aug 31, 1999
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N/A
app pub date -
Apr 21, 1998
filing date -
Apr 21, 1998
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Abstract
A self-biased power isolator system is disclosed that provides a fault tolerant power system without the need for auxiliary power. Enhancement-mode MOSFET 120 includes a drain coupled to a first node, a source coupled to a second node, and a gate. Amplifier 50 includes inputs for comparing the voltages from the first and second nodes and an output coupled to the gate of MOSFET 120 by which amplifier 50 controls the state of enhancement-mode MOSFET 120. Amplifier 50 further includes a positive power input coupled to the second node and a negative power input coupled to ground. In one embodiment, the first node is operable to be coupled to a power supply 10 and the second node is operable to be coupled to a load 18. A further embodiment allows the architecture to be replicated, each coupled at the second node to provide an N+1 fault tolerant power system.
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