Method and system for identifying failure point
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United States of America Patent
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Aug 31, 1999
Grant Date -
N/A
app pub date -
Jul 29, 1997
filing date -
Jul 29, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A failure point identifying method applicable to various defects and capable of promptly identifying a defect point. An LSI tester 4 sequentially impresses test vectors stored in a test vector file 1 across input terminals of a loaded LSI 5 to measure an Iddq value. A test vector number of a test vector which produced an abnormal Iddq value is delivered to a faulty block extractor 2. The faulty block extractor 2 performs logic simulation to find the input logic of each block of the LSI 5 when each test vector stored in the test vector file 1 is entered to the input terminals of the LSI 5. Moreover, a dump list associating each test vector number with the input logic is prepared from block to block. The faulty block is then identified based on the dump list of each block and the test vector number deliver from the LSI tester.
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