Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits

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United States of America Patent

PATENT NO 5943581
SERIAL NO

08964808

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Abstract

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An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes are etched in the epi layer to the N.sup.+ regions, and a selective wet etch removes the N.sup.+ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N.sup.+ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N.sup.+ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area. Lightly doped source/drain (LDD) areas, sidewall spacers and heavily doped source/drain contacts are formed for the FETs. A node strap is formed between one source/drain contact and the node contact to make good electrical contact. An insulating layer is deposited having bit line contact holes, and a second polycide layer is patterned to form the bit lines for the DRAM.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lu, Chih-Yuan Hsinchu, TW 60 2459
Sung, Janmye Yang Mei, TW 34 1046

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