Programmable logic arrays
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United States of America Patent
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Aug 10, 1999
Grant Date -
N/A
app pub date -
Jul 1, 1997
filing date -
Jul 13, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A programming or function-setting cell for a field programmable gate array utilizes ferroelectric capacitors connected to the nodes of a latch circuit to retain charge representing the state of the cell so that, following a power loss or a specific event upset, the programming information held by the latch circuit may be reinstated. The latch circuit comprises a pair of inverters having their inputs and outputs cross-coupled by way of respective switching transistors, and the capacitors are connected between the nodes and a common plate conductor normally held at a potential intermediate the supply potentials for the inverters.
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