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Abstract

An add/compare/select (ACS) processor in a Viterbi decoder is disclosed. The ACS processor comprises a plurality of processing elements for receiving two path metrics and two branch metrics, comparing each added values, and outputting two decision bits and two state metrics according to the compared result; a grouping unit for grouping N number of processing elements for corresponding N number of states into K number of units using the same state metrics and the same branch metrics; a multiplexer for multiplexing L (L=2K) number of path metrics provided from the grouping unit into two path metrics according to a predetermined clock signal, and outputting them to a corresponding processing element; a first demultiplexer for receiving two decision bits outputted from the corresponding processing element, and demultiplexing them into L number of decision bits according to the clock signal; and a second demultiplexer for receiving two state metrics outputted from the corresponding processing element, and demultiplexing them into L number of state metrics according to the clock signal. Hence, the size of the hardware for ACS processor significantly decreases by having the above structure.

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First Claim