Memory with bit line discharge circuit elements

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5926425
SERIAL NO

08941564

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A memory which solves a problem of a conventional memory in that it was difficult for the conventional memory to shorten the fall time of its output signal without increasing its size. The number of paths is increased for discharging each of read bit lines by connecting to each of the read bit lines one or more additional transistors for discharging the read bit line, and by utilizing the transistors associated with other read bit line or lines to discharge the particular read bit line. The additional transistors can be provided between the existing transistors. This makes it possible to shorten the discharge time without increasing the size of the memory.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
RENESAS SYSTEM DESIGN CO LTD5-20-1 JOSUIHON-CHO KODAIRA TOKYO 187-8588

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Morimoto, Tatsuo Tokyo, JP 15 135

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation