Silicon layer arrangement for last mask programmability
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United States of America Patent
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Jul 20, 1999
Issued Date -
N/A
app pub date -
Jul 15, 1997
filing date -
Jun 7, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for fabricating an application specific integrated circuit (ASIC) from a multitude of silicon layers, including upper silicon layers and lower silicon layers. A processor for performing defined calculations and a random access memory (RAM) for storing a plurality of variable data values are formed in the lower layers of the application specific integrated circuit. A read only memory (ROM) is formed in the uppermost layer of the application specific integrated circuit using a metal mask. The plurality of control functions and constant data values stored in the read only memory are required for operation of a particular type of battery with a particular type of battery chemistry, such as a rechargeable nickel metal hydride battery, or a rechargeable lithium ion battery. The invention allows one core ASIC to be programmed into several separate final products, each with a different last mask ROM code layer. The method allows a wafer lot to be processed up to the last mask, and then one of several finishing options can be selected.
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