Method and apparatus for parallel access to consecutive TLB entries
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United States of America Patent
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Jul 13, 1999
Grant Date -
N/A
app pub date -
Aug 1, 1995
filing date -
Aug 1, 1995
priority date (Note) -
Expired
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Abstract
Apparatus and method for enabling substantially simultaneous access to consecutive entries in an addressable translation memory. The addressable translation memory may be either direct mapped or multi-way set associative. An address decoder receives input address signals and generates output select signals. Each input address signal and each output select signal corresponds to one of the registers in the translation memory. The invention includes a plurality of primary select lines, each of which transmits one of the output select signals to its corresponding register. The invention also includes a plurality of secondary select lines, each of which transmits an output select signal corresponding to a particular register to a second register, the particular register and the second register storing consecutive entries in the translation memory. The particular register and the second register receive the output select signal substantially simultaneously.
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