Fault tolerant memory system
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United States of America Patent
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Jun 29, 1999
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N/A
app pub date -
Jan 5, 1998
filing date -
Jan 5, 1998
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Abstract
A fault tolerant memory system having a triple bit error correction and quadruple bit error detection capability is disclosed using control logic coupled to multiple decoders each having single bit error correction/double bit error detection capabilities. The memory system can also be provided with a sparing system which provides an additional memory device to circumvent failures in individual memory devices. The memory system is suited for severe environments such as computing systems operating in outer space.
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