Importance

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Abstract

A memory array includes a plurality of columns, each of said columns including a predetermined number of memory cells. A write driver for generating a signal which facilitates the writing of data to one or more of said memory cells is provided and has coupled to an output terminal thereof a write data line. The write data line, along which signals generated by the write driver propagate to selected memory cells, includes a plurality of column nodes. The columns are divided into groups, where each group contains columns bearing consecutive column addresses. One-half the columns in a first group, which bear the first column addresses, are associated with those column nodes closest to the write driver, while the other half of the columns in the first group, which bear the next consecutive column addresses, are associated with the column nodes furthest from the write driver. One-half the columns in a second group, which bear the next consecutive column addresses, are associated with the next available column nodes closest to the write driver, while the other half of the columns in the second group, which bear the next consecutive column addresses, are associated with the next available column nodes furthest from the write driver.

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First Claim