Low power set associative cache memory
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United States of America Patent
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Jun 15, 1999
Grant Date -
N/A
app pub date -
Jan 25, 1993
filing date -
Jan 25, 1993
priority date (Note) -
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Abstract
A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus.
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