Multi-bit semiconductor memory device allowing efficient testing
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United States of America Patent
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Jun 15, 1999
Grant Date -
N/A
app pub date -
Dec 10, 1997
filing date -
Jun 5, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Data supplied to a particular data input/output terminal is selected and the selected data is subjected to logic change for each memory cell based on mode setting data from a changing mode setting circuit and is simultaneously written into memory cells simultaneously selected in a memory array. After a reading logic changing circuit changes the data of these simultaneously selected memory cells in the same manner as the writing logic changing circuit does, a coincidence/non-coincidence among the logics of these data is determined, and a signal representing a logic in coincidence is output if a coincidence is found. Thus, testing can be achieved at a high speed and accurately, using test data having various patterns, without increasing the number of data input/output terminals used in the testing operation.
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