Method for making a vertically redundant dual thin film transistor
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United States of America Patent
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Jun 1, 1999
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app pub date -
Sep 15, 1997
filing date -
Feb 28, 1996
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Abstract
A thin film transistor having two vertically stacked channels and dual gate non-photosensitive structure, where the source drain to bottom gate structure is self-aligned. This structure occupies the same area on a substrate as a conventional single gate thin film transistor. This invention also discloses a process for manufacturing a dual gate structure with a simple three mask procedure.
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