Method of forming N- and P-channel transistors with shallow junctions

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United States of America Patent

PATENT NO 5897364
SERIAL NO

08668711

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A method for forming N- and P-channel transistors having shallow junctions in an integrated circuit device is described. A semiconductor substrate is provided having active regions separated from one another by isolation regions wherein there is a N-channel active region and a P-channel active region and wherein gate electrodes and associated lightly doped source and drain regions have been formed in each of the active regions. A layer of borosilicate glass is deposited overlying the semiconductor substrate. A photoresist mask is formed over the P-channel active region. The borosilicate glass layer is etched away where it is not covered by the photoresist mask thereby leaving the borosilicate glass layer only overlying the P-channel region. The photoresist mask is removed. A layer of phosphosilicate glass is deposited overlying the semiconductor substrate. The semiconductor substrate is heated whereby boron ions within the borosilicate glass layer are driven into the semiconductor substrate in the P-channel region to form heavily doped P-channel source and drain regions and whereby phosphorus ions within the phosphosilicate glass layer are driven into the semiconductor substrate in the N-channel region to form heavily doped N-channel source and drain regions. The phosphosilicate layer is planarized to complete the formation of N- and P-channel transistors in the fabrication of an integrated circuit device.

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Patent Owner(s)

Patent OwnerAddress
CHARTERED SEMICONDUCTOR MANUFACTURING PTE LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738406

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Inventor Name Address # of filed Patents Total Citations
Pan, Yang Singapore, SG 310 4868

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