Application of fast etching glass for FED manufacturing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5893787
SERIAL NO

08805877

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The microtip housing cavity in a cold cathode display was formed by selecting for the dielectric layer surrounding it a material whose etch rate (for the same etchant) was 3 to 20 times faster than the etch rate of the gate layer. Specifically, a gaseous etchant that included CHF.sub.3, CH.sub.4, CO, or CO and C.sub.4 F.sub.8 was used to form the cavity in a layer consisting of silicon oxide containing between about 3 and 10 weight % boron and between about 3 and 10 weight % phosphorus, deposited by chemical vapor deposition at pressures somewhat less than atmospheric (commonly referred to as SABPSG or sub-atmospheric boro-phosphosilicate glass). The gate layer consisted of phosphorus-doped polysilicon. Using this combination, once the gate opening had been etched, etching of the cavity proceeded very rapidly with little increase in the width of the gate opening. Thus the cavity was formed in a single mask, single etchant process.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
CHARTERED SEMICONDUCTOR MANUFACTURING PTE LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738406

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Lap San Francisco, CA 159 4868
Chooi, Simon Singapore, SG 97 2270

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation