Synchronous semiconductor memory device operable in a plurality of data write operation modes
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United States of America Patent
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Apr 6, 1999
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N/A
app pub date -
Dec 1, 1997
filing date -
May 29, 1997
priority date (Note) -
Expired
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Abstract
A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.
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