Logical block for a Viterbi decoder
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United States of America Patent
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Mar 23, 1999
Grant Date -
N/A
app pub date -
Oct 3, 1996
filing date -
Oct 21, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A logical block is disclosed for decoding a data sequence encoded by a convolutional code, in which a given number of states are to be evaluated. These given states are assigned the given number of state memories which store an associated path and an accumulated distance value. The given number of state memories are associated with parallel processing blocks which each have, as the smallest group to be processed in parallel, two state memories to be read from first and second parallel processing blocks, and two state memories to be written into third and fourth parallel processing blocks. Optimum memory organization permits simple parallel processing and reduction in circuit complexity.
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Patent Citation Ranking
- 6 Citation Count
- H03M Class
- 1.72 % this patent is cited more than
- 26 Age