Preventing corruption in a multiple processor computer system during a peripheral device configuration cycle
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United States of America Patent
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Feb 2, 1999
Grant Date -
N/A
app pub date -
Dec 17, 1996
filing date -
Dec 17, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.
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