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Abstract

A series delay generator for imposing a programmable delay on the timing edges of an incoming waveform is disclosed. The magnitude of the imposed delay is proportional to the value of a binary programming word. The series delay generator is implemented as a series of delay cells, each of which can be programmed into two delay states, a maximum delay and a minimum delay. The magnitude of the maximum and minimum delays can be set and calibrated using an analog tuning voltage. The series of delay cells can be segmentized in order to provide pipelined operation. The series delay generator is therefore capable of processing more than one timing edge at a time, permitting its minimum reprogramming time to span and even exceed the maximum delay span of the generator. A delay cell is also disclosed that uses a differential input and a digitally controlled current balance circuit to advance and retard the zero crossings of the incoming waveform and its inverse. The output is fed back to the digital control input to reduce pulse width distortion of the incoming waveform. Cells using a double-balanced and single-balanced current balance circuit are disclosed.

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First Claim