Data processor with branch target address generating unit
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United States of America Patent
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-
Dec 8, 1998
Issued Date -
N/A
app pub date -
Sep 29, 1995
filing date -
Feb 7, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.
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