Multiprocessor system employing an improved self-coded distributed interrupt arbitration technique
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United States of America Patent
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Dec 1, 1998
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N/A
app pub date -
May 31, 1996
filing date -
May 31, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multiprocessor system has a shared bus and a plurality of processor modules, wherein the shared bus includes an interrupt bus and each of the processor module contains an interrupt controller. The interrupt controller for performing an interrupt bus arbitration includes an interrupt bus arbiter. The interrupt bus arbiter has N number, e.g., 8 of arbitration cells, wherein each cell simultaneously receives a corresponding bit of the arbitration information, lower bits of the corresponding bit and corresponding lower bits of the wired-ORed interrupt bus data to generate an interrupt bus gain signal when the corresponding bits represent one logic state and the lower bits represent the other logic state; and a decision circuit connected to the arbitration cells for generating an interrupt bus gain decision signal when the interrupt bus gain signal is received.
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