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Abstract

A system and method for provides a generating a plurality of clock phases from a clock signal in a telecommunications cross connect system. The digital delay circuit includes a plurality of delay elements connected in series, each delay element connected to a sampling element, the output of the sampling elements sent to a multiplexor. The total number of delay elements comprises a number that produces a worst case delay equal to or greater than the period of the clock signal. The delay elements receive the rising edge of the clock signal. The delayed rising edges are sent to the sampling elements. The sampling elements send outputs to the multiplexor for determining the number of delay elements transitions by one cycle of the clock signal. A programming device can be coupled to the multiplexor to request from the multiplexor a particular phase of the clock signal. The multiplexor can select the appropriate delay device to generate the particular phase of the clock signal.

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First Claim