Importance

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Abstract

Methods for packaging TAB-BGA integrated circuits are disclosed, which mainly include steps of providing a double-sided polyimide; forming first dry film layers; sequentially performing a multi-layer electroplating operation of electro-coppering, electronickelling, gold plating and electronickelling again (or electronickelling and gold plating, or electro-coppering and electronickelling); removing the first dry film layers; serving a lower second dry film layer as a mask for etching a bottom thin copper layer to define a plurality of predetermined openings; serving the bottom thin copper layer as a mask for applying a laser etching operation to the polyimide substrate to define holes without totally penetrating the polyimide substrate; applying an electrolytic plating operation to the holes for forming protruding contacts; etching the exposed top thin copper layer and/or removing a nickel-electroplated layer; and respectively defining a chip installation hole and a plurality of through holes by performing a laser drilling operation, and a chip is attached to the two electroplated multi-layer (or double-layer) protrusions beside the chip installation hole by using a single point bond method, in which reducing the external contacts and minimizing the package dimension are achieved.

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First Claim