Data processor with dynamic and selectable interconnections between processor array, external memory and I/O ports
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United States of America Patent
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Nov 3, 1998
Grant Date -
N/A
app pub date -
Dec 15, 1995
filing date -
Dec 15, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processor intended for a single instruction, multiple data mode operation includes memory that is external to the processor array, and a controller that dynamically and selectably interconnects multiple edges of the processor array with the memory and with I/O ports. A separate controller module is provided for each memory channel, and interconnects with corresponding edge processing elements of the processor array. The controller modules for the different channels are independent of each other, as are the channel memories. In the case of a rectangular processor array, each channel memory can be implemented with only three memory stores that are interconnected with the four edges of the processing array and the I/O ports through the channel controller module, yet for most algorithms provide a throughput that is comparable to that resulting from the use of four memory stores.
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