Serial bit rate converter embedded in a switching matrix
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United States of America Patent
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Oct 6, 1998
Grant Date -
N/A
app pub date -
Mar 11, 1996
filing date -
Jul 16, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The serial-to-parallel converters are staggered length shift registers. The output side of the switching matrix can be similarly configured.
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