Synchronization and battery saving technique
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United States of America Patent
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Sep 22, 1998
Grant Date -
N/A
app pub date -
Dec 28, 1994
filing date -
Dec 28, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A synchronization apparatus in a selective call receiver comprised of a digital variable bandwidth phase locked loop with means to simultaneously detect the synchronization code word, means to generate a binary code from a register representative of lock quality, means to increment or decrement the lock quality register, means to sum the lock quality binary code into a phase error register, whereby the polarity of the sum is controlled by a phase comparison of the a local clock with the received data, and whereby the under or over flow of the phase error register determines the direction of a phase adjustment to the local bit clock generator.
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