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Abstract

A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses. Additionally, a data input/output unit performs an arithmetic operation on data transferred from an external memory to a vector register, wherein the result of the arithmetic operation, upon completion, is transferred from the vector register to the external memory for storage. The data input/output unit has a data holding unit storing m-bit data units and rearranges exactly in the original order n pieces of m/n-bit data when n pieces of m/n-bit data are loaded from an external memory and then stored back into the external memory.

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