Clock frequency synthesis using delay-locked loop
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United States of America Patent
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Sep 8, 1998
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N/A
app pub date -
Aug 29, 1997
filing date -
Nov 2, 1995
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Abstract
A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.
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