Interface between a memory having a given number of address inputs and a processor having fewer address outputs, and processor and memory equipped accordingly
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United States of America Patent
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-
Sep 1, 1998
Grant Date -
N/A
app pub date -
Nov 21, 1995
filing date -
Nov 24, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An interface between a memory that has 'n' address bit inputs and a processor which has 'p' address bit outputs (where p
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