Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices
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United States of America Patent
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Sep 1, 1998
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N/A
app pub date -
Nov 8, 1995
filing date -
Nov 8, 1995
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Abstract
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.
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