Importance

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Abstract

A flash memory with a flexible erasing size includes a first bank of flash transistors and a second bank of flash transistors. Each bank of flash transistors forms a plurality of rows and a plurality of columns, each transistor having a gate, drain and source, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline, where the wordline decoder includes a wordline latch configured to latch the selected wordline. A sourceline decoder is coupled to the sourcelines and configured to receive a sourceline address signal and to decode the sourceline address signal to select a sourceline, where the sourceline decoder includes a sourceline latch configured to latch the selected sourceline. A bitline decoder is coupled to the bitlines and configured to receive a bitline address signal and to decode the bitline address signal to latch a selected bitline, where the bitline decoder includes a bitline latch configured to latch the selected bitline.

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First Claim