Current memory cell having bipolar transistor configured as a current source and using field effect transistor (FET) for current trimming
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United States of America Patent
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Aug 11, 1998
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N/A
app pub date -
Apr 18, 1997
filing date -
Apr 18, 1997
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Abstract
A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.
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