Semiconductor device with first and second wells which have opposite conductivity types and a third well region formed on one of the first and second wells
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United States of America Patent
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Aug 4, 1998
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N/A
app pub date -
Nov 20, 1996
filing date -
Nov 22, 1993
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Abstract
Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.
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