Importance

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Abstract

A gray-scale level signal V.sub.a, which is applied to each pixel on a selected gate bus, is added, with its polarity inverted every frame period, to the first and second source bias voltages V.sub.S+ and V.sub.S-which are generated alternately every frame period, and the resulting voltages are each provided as a source voltage V.sub.S to respective source buses. On the other hand, a gate voltage V.sub.G, which is applied to each gate bus, includes a period of a high-level gate pulse which turns ON a thin film transistor during about one horizontal scanning period H in each frame period, a gate bias period during which either one of first and second gate bias voltages, which alternate every frame period, immediately precedes the rise of the gate pulse, and a low-level period except these periods. The gate voltage is applied to the respective gate buses so that the gate pulses provided thereto are sequentially displaced one horizontal scanning period apart. The gate bias period of an i-th row has a span from the time of the rise of the gate pulse to time instant preceding the fall of the gate pulse of the immediately preceding (i-l)th row. By this, the first and second gate bias voltages V.sub.x1 and V.sub.x2, which are provided to the i-th row, are alternately added to the gate voltage in positive and negative write periods in AC-wise driving of the pixels on the (i-l)th row, reducing flicker in the liquid crystal display.

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First Claim