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Abstract

A data processing system including dynamic random access memory (DRAM) in a bus architecture is disclosed. A controller is included in the system which unconditionally generates the row address strobe (RAS.sub.--) and column address strobe (CAS.sub.--) signals to the DRAM responsive to the initiation of a bus cycle. The controller also includes a decoder which decodes the address value during the DRAM cycle initiated by the RAS.sub.-- and CAS.sub.-- signals, and generates the select signals (for example, output enable and write enable signals, depending upon whether the access is a read or a write) if the address value indicates that the bus operation is to be a DRAM access. No select signal is generated in the event that the bus operation is not a DRAM access, so that the DRAM operation initiated by the RAS.sub.-- and CAS.sub.-- signals remains an internal operation and does not affect the common data bus. The effective DRAM system cycle time is reduced because all bus operations assume that the operation is a DRAM access; no DRAM access is delayed by the decoding of the address value.

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First Claim