ATM cell synchronous system
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United States of America Patent
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Jun 23, 1998
Grant Date -
N/A
app pub date -
Sep 5, 1995
filing date -
Sep 2, 1994
priority date (Note) -
Expired
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Abstract
An asynchronous transfer mode (ATM) cell synchronizing method and circuit used in a digital network system in which: an 8 bit ATM cell stream of a received signal is inputted into a five-stage D flip-flop and outputted to a first adder (exclusive OR) circuit through a remainder operation circuit; the adder circuit evaluates exclusive OR of the output of the remainder operation circuit and the inputted 8 bit ATM cell stream, the result of such an evaluation is inputted into a one-stage D flip-flop through a second adder; and the output of this one-stage D flip-flop is inputted into a CRC arithmetic operation circuit having a generating polyominal X.sup.8 +X.sup.2 +) X+1 and also into a decoder. The output of the CRC arithmetic operation circuit is inputted back to the second adder, and a cell synchronizing pulse is outputted from the decoder.
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